Hi, I'mParth R. Doshi
Computer Engineer & Systems Architect
Bridging hardware and software to build innovative solutions
About Me
Who I Am
I'm a Computer Engineering graduate student at Purdue University with a passion for both hardware and software innovation. With experience at leading tech companies like Google and AMD, I specialize in building robust systems that bridge the gap between hardware architecture and software development.
My work spans from designing full-custom VLSI circuits and CPU verification to developing cloud-native software and contributing to open-source projects. I'm particularly interested in computer architecture, systems programming, and creating efficient solutions that push the boundaries of performance.
When I'm not working on projects, you can find me exploring new technologies, contributing to open-source communities like OpenTelemetry and SigStore, or diving deep into the latest advances in computer architecture and AI/ML.
Education
Boiler Up! Hammer Down!
Master of Science: Computer Engineering
Purdue University, College of Engineering
Relevant Coursework:
Bachelor of Science: Computer Engineering
Purdue University, College of Engineering
Relevant Coursework:
Work Experience
Industry experience at leading technology companies, working on cutting-edge hardware and software solutions
Full-Time Positions
L3 Software Engineer
Persistent Disks, Google Cloud
Internships
Software Engineer Internship
Google Cloud
CPU Post-Silicon Verification Engineer Internship
AMD
Software Engineer Internship
Datamatics Global Services
Featured Projects
A showcase of my hardware and software projects
Hardware Projects
Computer architecture, VLSI design, and hardware verification projects
High-Performance 8-bit Wallace Tree Multiplier
Nov 2025 - Dec 2025
CMOS VLSI, Full-Custom
Designed a full-custom 8-bit Wallace Tree multiplier at the transistor level using CMOS VLSI. Implemented multi-stage Wallace Tree reduction and a ripple-carry adder with mirror-topology full adders, completing a DRC/LVS-clean schematic-to-layout flow in Cadence Virtuoso. Achieved 2.47 ns worst-case delay and 765 fJ energy post-layout.
RISC-V 5 Stage Pipelined CPU
Aug 2023 - Dec 2024
Computer Design and Prototyping
Designed and implemented a 5-stage pipelined RISC-V CPU supporting variable-latency RAM and hazard resolution, enabling correct execution under memory stalls and improving pipeline efficiency through forwarding and stall logic. Integrated ALU, control unit, memory arbiter, and request logic into the data path based on the von Neumann model, and verified functionality using MIPS assembly tests on QuestaSim, synthesizing the design onto an Altera DE2 FPGA for hardware validation.
Victim Cache Design & Policy Evaluation in gem5
Nov 2025 - Dec 2025
Computer Architecture
Designed and implemented a configurable Victim Cache in gem5 by adding an any-miss no-allocate policy to enforce mostly-exclusive behavior. Modified cache allocation logic at the MSHR level to ensure the VC populates only via L1 evictions. Evaluated baseline, mostly-exclusive, and no-allocate VC designs across SPEC workloads, analyzing IPC and miss-rate tradeoffs.
Waiting Instruction Buffer (WIB) Simulation in gem5 O3 CPU
Oct 2025 - Dec 2025
Computer Architecture
Designed and implemented a virtual Waiting Instruction Buffer (WIB) in gem5's out-of-order CPU to isolate load-miss-dependent instructions from the active issue queue. Extended dependency tracking, wake-up, and scheduling logic to model hardware WIB behavior with minimal simulator intrusion, preserving cycle accuracy. Demonstrated up to 2× speedup on memory-latency-bound SPEC workloads.
Audio Synchronizer
Jan 2023 - May 2023
Embedded Systems
Designed a Verilog-based audio speaker to play, record, and store four sounds—kick, clap, hi-hat, snare—using state machines and integrated submodules such as audio sequencers and clock dividers.
Software Projects
Software engineering, systems programming, and AI/ML projects
High-Performance Datacenter Network Simulator
Aug 2024 - Dec 2024
Datacenter and Cloud Networks
Built a high-fidelity datacenter network simulator modeling a 54-host, 3-tier Fat-Tree topology with flow-level ECMP routing and implemented packet-level tracing and topology-aware visualization. Integrated DCTCP congestion control with ECN marking and RTT-based cwnd adjustment and implemented delta-driven flowlet load balancing, achieving up to 5× throughput gains and 60% lower latency variance in incast workloads.
OpenTelemetry (Open-Source Software)
Aug 2024 - Dec 2024
Advanced Software Engineering
Enhanced telemetry data generation for cloud-native software by integrating popular logging libraries into the OpenTelemetry framework. Performed security reviews and penetration testing, implementing 'structlog' and 'log-guru' handlers for monitoring and troubleshooting.
SigStore Rekor (Open-Source Software)
Aug 2024 - Dec 2024
Advanced Software Engineering
Developed secure systems to avoid supply chain attacks by formulating a suite of strategies for integration into SigStore Rekor. Conducted risk analysis and vulnerability testing, creating trigger mechanisms for logging alerts and email notifications on malicious actions using consistency protocols.
JOS: User-Centric Operating System Framework
Jan 2024 - May 2024
Operating Systems
Developed a Unix-like operating system with an ExoKernel architecture, implementing key features like process and memory management, file systems, and networking. Emphasized user-level library implementation using C++ and GDB to enhance system flexibility and modularity.
Software Defined Network
Jan 2024 - May 2024
Computer Network Systems
Engineered an advanced Software-Defined Networking (SDN) system with Python, featuring centrally controlled switches and a dynamic topology system that adapts quickly to network changes. Integrated Dijkstra's algorithm for optimal routing efficiency.
Image Editing Diffusion Models
Aug 2023 - Dec 2023
Artificial Intelligence
Enhanced image editing capabilities using the InstructPix2Pix (IP2P) model adapted for text and image inputs, leveraging Hugging Face's tools. Fine-tuned on RT1's dataset for better spatial reasoning and object recognition using custom PyTorch scripts on Google Collaboratory Pro.
AES Image Encryption
Jan 2023 - May 2023
Computer Security
Implemented AES image encryption using ANSI X9.31 PRNGs for cryptographically secure key generation in Counter mode with Python.
Bike Traffic Prediction
Jan 2023 - May 2023
Python for Data Science
Analyzed bike traffic across NYC bridges to estimate traffic flows using Python and the SKLearn module. Applied machine learning techniques like Ridge Regression and Five-Fold Cross Validation for model tuning and used KNN classification to correlate weather conditions with bike traffic patterns.
Firewall Design
Jan 2023 - May 2023
Computer Security
Designed a custom firewall for Linux using IPv4 packet filtering and network address translation tools to set up, maintain and inspect the tables of IP packet filter rules.
Dijkstra Pathfinding Algorithm
Aug 2022 - Dec 2022
Data Structures and Algorithms
Implemented the Dijkstra Shortest Path Algorithm in C on a cost matrix, utilizing min-heap priority queues and 2D arrays to efficiently find the fastest paths, achieving a runtime of 0.150s for a 1000x1000 matrix.
My Skills
A collection of technologies and tools I work with to bring ideas to life
Technologies I Work With
Awards & Achievements
Recognition for academic excellence and outstanding performance at Purdue University
Charles W. Brown Scholarship in Electrical and Computer Engineering
Purdue University
Amount: $6,000
Eli Shay Scholarship in ECE
Purdue University
Amount: $8,000
Dean's List and Semester Honors
Purdue University
7x Recipient
My Hobbies
Beyond code and circuits, these are the passions that fuel my creativity
Soccer
Passionate about the beautiful game, following international leagues and enjoying both playing and watching.
Table Tennis
Quick reflexes and strategic gameplay on the ping pong table.
Working Out
Maintaining an active lifestyle through strength training and fitness routines.
Track Sprinting
Competing in 100m and 200m sprints, focusing on speed, power, and technique.
Exploring Nightlife & Culture
Discovering live entertainment, cultural events, and vibrant nightlife scenes around the world.
Travelling
Exploring diverse cultures, cuisines, and experiences across the globe
Get In Touch
Have a project in mind? Let's work together to bring your ideas to life.